This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-075065, filed Mar. 19, 1999; No. 11-250509, filed Sep. 3, 1999; and No. 2000-001833, filed Jan. 7, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor apparatus, and more particularly to a semiconductor memory device having a multibank structure which incorporates a redundant circuit for relieving a defect memory cell.
A semiconductor memory device has a redundant system employed to improve the manufacturing yield by substituting a redundant cell for a defect cell to relieve the defect cell when a defect cell has been detected in a portion of memory cells as a result of a test of a memory cell array. A redundant system which is employed usually at present uses a method with which one or more cell arrays including the defect cell is, as a unit, replaced with a spare element having the same size as that of the cell array (replacement of a cell array unit).
Address information of the cell array unit including the defect cell is stored in a nonvolatile memory device including fuses. Since address information is composed of a plurality of bits, a fuse set including a plurality of fuses corresponding to the plurality of bits is employed. The fuse set is usually one-to-one correspond to the spare element. Fuse sets, the number of which is the same as that of the spare elements, are provided in a chip. When the spare element is used, fuses in the fuse set corresponding to the spare element are cut in accordance with address information.
Since the redundant system requires the redundant circuit including the spare elements and the fuse sets, the area of the memory chip is enlarged excessively. Since the number of defects, which can be relieved, and the area of the redundant circuit satisfy a trade-off relationship, a variety of redundant systems substantially capable of improving the area efficiency have been suggested.
For example, a flexible redundant systems (xe2x80x9cFaulty-Tolerant Design for 256 Mb DRAMxe2x80x9d(refer to IEEE JOURNAL of SOLID-STATE CIRCUITS, VOL. 31, No. 4, April 1996) suggested by Kirihata et al. is known. The foregoing method arranged such that one spare element covers a wide cell array region is able to relieve a faulty state where defect cells are eccentrically present in a portion of a chip similarly to a state where faults are present uniformly. Therefore, the number of the spare elements can be reduced, causing the area efficiency of the redundancy circuit to be improved. The foregoing method is effective in a case where the number of faults per chip has been detected or estimated.
On the other hand, a memory chip has been developed in which the memory cell array is divided into sections. For example, a memory chip is known which includes a plurality of banks arranged to simultaneously be activated.
In a memory chip of the foregoing type, the row spare element for relieving a defect memory cell in a row unit cannot be used across the bank. Therefore, a limitation is imposed such that a spare element must be prepared for each bank. As the number of the banks is enlarged, the number of sections of the memory cell array in the chip is enlarged. Hence it follows that the area of the cell array region which can be covered by one spare element is reduced.
When the spare element is provided for each bank, the possibility that defects of the memory cell eccentrically occur is raised considerably as the capacitance of the memory is enlarged. To maintain a high efficiency percentage, the number of the spare elements to be included in each bank must be enlarged. As a result, the area of the chip is enlarged excessively.
To relieve a defect cell even if defects are eccentrically present in a portion of the memory cell array in a case where the spare element can cover only a narrow region as described above, the spare element must be provided for each of the narrow cell array region. As a result, the spare elements are mounted on a chip by a number considerably larger than an average number of defects per chip. Therefore, the overall area efficiency of the chip deteriorates.
The conventional method with which the spare elements and the fuse sets are one-to-one corresponded encounters increase in the number of fuse sets as the number of the spare elements is increased. Since the fuse set generally requires an area larger than the area required for the spare element, the area efficiency of the redundant circuit excessively deteriorates.
To overcome the foregoing problem, a method is known with which the number of the fuse sets which is larger than an estimated number of defects in the overall cell array can be made to be smaller than the number of all of the spare elements. Specifically, the relationship of the corresponding information with plurality of spare row decoders in each bank is included in each fuse set. Thus, the necessity for causing each fuse set to one-to-one correspond to the spare element can be eliminated.
A portion of conventional DRAM includes a type having a structure that the overall cell array is sectioned into 16 banks. Moreover, eight spare elements are provided for each bank to cope with a state where defects are eccentrically present. Assuming that the average defects in the overall cell array is about 20, twenty eight fuse sets which is smaller than the number of all of the spare elements which is 128 are used to cope with a state where defects are uniformly dispersed or defects are present eccentrically. Since the spare elements, the total number of which is 128, are provided, the area efficiency of the spare element is unsatisfactorily low.
Note that the number of banks increases in proportion to the enlargement of the capacitance of the memory. The necessity for increasing the number of the banks is not raised in the future. The increasing rate of the number of the banks with respect to the enlargement of the capacitance of the memory will be lowered. Since the lengths of the bit line and the word line have upper limits, the size of the sub-array constituting the bank has an upper limit. Hence it follows that the number of the sub-arrays is increased. To be adaptable to the foregoing trend, a structure is employed in which when a certain bank has been activated, a sub-array belonging to the bank and maintained at a non-active state is present.
A semiconductor memory having the structure that the active sub-arrays and non-active sub-arrays belonging to the same bank are present suffers from a problem in that the area of the chip is excessively enlarged if a multiplicity of spare elements are provided for each sub-array.
Since the defect is not fined when the device is fined, a portion of defects has a relatively large width (area). Thus, use of a plurality spare elements is sometimes required.
The method with which the number of the fuse sets is made to be smaller than the total number of the spare elements involves a fact that consumption of a plurality of the spare elements causes the fuse sets to, of course, be consumed by the same number. Therefore, fewer fuse sets sustain greater damage owing to a defect having a width larger than the spare element.
FIG. 21 collectively shows defect example A and B caused from defects which are possible to occur in one bank.
The defect example A is an example in which a defect having a large area corresponding to two word lines is relieved by using one spare element. In the foregoing case, one fuse set is used.
The defect example B is an example in which two spare elements are required to relieve a defect having a large area corresponding to two word lines. In the foregoing case, two fuse sets are used. AS the device is fined, the defect example B increases. In an extreme case in which all of twenty estimated defects traverse the boundary of the unit for the substitution, insufficiency of the fuse sets occurs with reliability in spite of low possibility of insufficiency of the number of the spare element.
If the pattern is fined considerably as compared with the width of the defect, a state is realized in that the number of the fuse sets cannot be reduced in spite of requirement for decreasing the fuse sets which requires a large area.
As described above, the conventional DRAM having the multibank structure suffers from a problem in that increase in the number of the spare element causes the area efficiency to deteriorate.
Also a conventional DRAM having the multibank structure in which each bank is composed of a plurality of sub-arrays is arranged such that an independent spare element is provided for each sub-array of each bank to cope with eccentric presence of defects. Therefore, increase in the number of the spare element causes the area efficiency to deteriorate.
The conventional DRAM having the multibank structure suffers from a problem in that insufficiency of the fuse sets occurs when a state in which the defect traverse the boundary of the spare element which is the unit for the substitution.
To achieve the problems experienced with the conventional structures, an object of the present invention is to provide a semiconductor memory device which is capable of coping with a case where defects are present eccentrically in the overall cell array even if the number of spare elements corresponding to a plurality of units of a memory cell array which has been fined in recent years is reduced and reducing the total number of the spare elements while the relieving ratio and relieving degree of freedom are being maintained so as to improve the area efficiency of a redundant circuit on a chip.
Another object of the present invention is to provide a semiconductor memory device which permits common use of a spare element provided for each sub-array of each bank in the same bank, which is capable of coping with a state where defect are present eccentrically in the overall cell array and reducing the total number of the spare elements while the relieving ratio and relieving degree of freedom are being maintained so as to improve the area efficiency of a redundant circuit on a chip.
Another object of the present invention is to provide a semiconductor memory device structured to enable one fuse set to perform substitution for a plurality of spare elements, preventing consumption of fuse sets when a defect having a large width is overcome and attaining satisfactory efficiency percentage without a necessity of increasing the fuse sets which require a large area.
According to a first aspect of the present invention, there is provided a semiconductor memory device comprising a first spare element provided for each of a plurality of units of a memory cell array; second spare elements in addition to the plurality of units; and circuits for selectively assigning the second spare elements to arbitrary units of the plurality of units.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of normal banks formed by dividing a memory cell array into a plurality of sections; first redundant cell arrays collectively provided as one spare bank so as to be substituted for a defect memory cell of the memory cell array; a plurality of second redundant cell arrays provided to correspond to the plurality of normal banks; normal decoders provided to correspond to the normal banks and arranged to select the row and column of the memory cell array in accordance with an input address; a first spare decoder for selectively operating the plurality of first redundant cell arrays; a plurality of second spare decoders for selectively and correspondingly operating the plurality of second redundant cell arrays; a first substitution-control signal line for supplying a first substitution-control signal for controlling the operation of the first spare decoder; a second substitution-control signal line for supplying a second substitution-control signal for controlling the operation of the plurality of second spare decoders; a plurality of first memory circuits in which information of the address of a defect memory cell and information as to which of the first redundant cell array and the second redundant cell array corresponds to each of the plurality of first memory circuits are previously stored to selectively output the first substitution-control signal or the second substitution-control signal in accordance with a detection result of the correspondence between the stored address of the defect memory cell and the input address and information of the correspondence with the first redundant cell array or the second redundant cell array; and a control circuit for controlling the normal decoder to be deactivated state when either of the first substitution-control signal line or the second substitution-control signal line is in an active state.
In the semiconductor memory device according to the second aspect of the present invention, the first memory circuit may comprise first storage circuits for previously storing information of the address of a defect memory cell and information as to which of the first redundant cell array and the second redundant cell array corresponds to each of the plurality of first memory circuits are previously stored; and a first output circuit which determines which of the first redundant cell array and the second redundant cell array corresponds to the first memory circuit in accordance with information stored in the first storage circuits to output the first substitution control signal or the second substitution control signal. The first storage circuit may comprise a plurality of first fuse device for storing each bit data of the address of the defect memory cell to correspond to a state of cut/non-cut; a second fuse device for storing one-bit data for instructing conduction of selection of the first redundant cell array to correspond to the state of cut/non-cut; and a third fuse device for storing one-bit data for instructing conduction of selection of the second redundant cell array to correspond to the state of cut/non-cut, and the first output circuit may comprise a comparison circuit for making a comparison between the stored address of the defect memory cell and the input address; a first AND gate which performs a logical process of an output representing a result of the comparison made by the comparison circuit and data stored in the second fuse device to output the first substitution control signal; and a second AND gate which performs a logical process of an output representing a result of the comparison made by the comparison circuit and data stored in the third fuse device to output the second substitution control signal.
According to a third aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of normal banks formed by dividing a memory cell array into a plurality of sections; a plurality of first redundant cell arrays provided as a plurality of spare banks so as to be substituted for a defect memory cell of the memory cell array; a plurality of second redundant cell arrays provided to correspond to the plurality of normal banks; normal decoders provided to correspond to the normal banks and arranged to select the row and column of the memory cell array in accordance with an input address; a plurality of first spare decoders corresponding to the plurality of the first redundant cell arrays to select and operate the plurality of the first redundant cell arrays; a plurality of second spare decoders corresponding to the plurality of the second redundant cell arrays to select and operate the plurality of the second redundant cell arrays; a plurality of first substitution-control signal lines for supplying a first substitution-control signal for alternatively controlling the operation of the plurality of the first spare decoders; a second substitution-control signal line for supplying a second substitution-control signal for controlling the operation of the plurality of the second spare decoders; a plurality of first memory circuits in which information of the address of a defect memory cell and information as to which of the first redundant cell array and the second redundant cell array corresponds to each of the plurality of first memory circuits are previously stored to selectively output the first substitution-control signal or the second substitution-control signal in accordance with a detection result of the correspondence between the stored address of the defect memory cell and the input address and information of the correspondence with the first redundant cell array or the second redundant cell array; and a control circuit for controlling the normal decoder to be deactivate when the plurality of first substitution-control signal lines or the second substitution-control signal lines are active.
In the semiconductor memory device according to the third aspect of the present invention, the first memory circuit may comprise first storage circuits for previously storing information of the address of a defect memory cell and information as to which of the first redundant cell array and the second redundant cell array corresponds to each of the plurality of first memory circuits are previously stored; and a first output circuit which determines which of the first redundant cell array and the second redundant cell array corresponds to the first memory circuit in accordance with information stored in the first storage circuits to selectively output the first substitution control signal or the second substitution control signal.
According to a fourth aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of normal banks formed by dividing a memory cell array into a plurality of sections; a plurality of first redundant cell arrays collectively provided as one spare bank so as to be substituted for a defect memory cell of the memory cell array; a plurality of second redundant cell arrays provided to correspond to the plurality of normal banks; normal decoders provided to correspond to the normal banks and arranged to select the row and column of the memory cell array in accordance with an input address; a plurality of first spare decoders corresponding to the plurality of the first redundant cell arrays to select and operate the plurality of the first redundant cell arrays; a plurality of second spare decoders corresponding to the plurality of the second redundant cell arrays to select and operate the plurality of the second redundant cell arrays; a plurality of first substitution-control signal lines for supplying a first substitution-control signal for correspondingly and selectively operating the plurality of first spare decoders; a second substitution-control signal line for supplying a second substitution-control signal for controlling the operation of the plurality of second spare decoders; a plurality of first memory circuits including first storage circuits which are provided to correspond to the plurality of first substitution-control signal lines and in which the address of a defect memory cell is previously stored and structured to selectively output the first substitution-control signal to the corresponding first substitution-control signal line in accordance with a detection result of the correspondence between the address of the defect memory cell stored in the first storage circuits and the input address; a plurality of second memory circuits including second storage circuits in which information of the address of a defect memory cell and information as to which of the first redundant cell array and the second redundant cell array corresponds to each of the plurality of first memory circuits are previously stored and arranged to selectively output the second substitution-control signal to the second substitution-control signal line in accordance with a detection result of the correspondence between the address of the defect memory cell stored in the second storage circuits and the input address and information of the correspondence with the plurality of second redundant cell arrays; and a control circuit for controlling the normal decoder to be deactivate when the plurality of first substitution-control signal lines or the second substitution-control signal line is active.
According to a fifth aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of memory banks which are formed by dividing a memory cell array into a plurality of sections and each of which is constituted by a plurality of sub-arrays; a plurality of spare elements which are provided for each of the sub-arrays and arranged to be substituted for a defect memory cell; a plurality of normal decoders which are provided to correspond to each of the sub-arrays and arranged to select the row of the sub-array in accordance with an input address; a plurality of spare decoders which are provided to correspond to each of the sub-arrays and arranged to correspondingly operate the plurality of spare elements; a plurality of bank selecting lines for selecting and instructing the plurality of memory banks; a plurality of normal-decoder control lines provided to correspond to the sets composed of a plurality of sub-arrays constituting the plurality of memory banks and arranged to select and instruct the normal decoders of the normal decoders and the spare decoders provided to correspond to the sub-arrays of each set; a plurality of spare-decoder control lines provided to correspond to the sets composed of the plurality of sub-arrays constituting the plurality of memory banks and arranged to select and instruct the spare decoders of the normal decoders and the spare decoders provided to correspond to the sub-arrays of each set; a plurality of spare-decoder selecting lines for alternatively selecting and controlling the plurality of spare decoders of each sub-array; and assigning circuits for selectively assigning the spare element of each sub-array to another sub-array belonging to the same bank.
In the semiconductor memory device according to the fifth aspect of the present invention, the assigning circuits may comprise a plurality of memory circuits in which information of the relationship between the address of the defect memory cell and the spare decoder made to one-to-one correspond to the address of the defect memory cell is previously stored, which make a comparison between the input address and the stored address of the defect memory cell to output a signal for selectively activating the plurality of spare decoder control lines and which outputs a signal for selectively activating the plurality of spare-decoder selecting lines in accordance with the stored address of the defect memory cell and the spare decoder when coincidence has been detected, and which outputs a signal for selectively activating the plurality of normal-decoder control lines when non-coincidence has been detected. Each memory circuit may comprise first storage circuits in which the address of the defect memory cell is stored; second storage circuits in which information of the correspondence with sub-arrays of a plurality of sets constituting the plurality of memory banks is stored; third storage circuits in which information of the correspondence with the plurality of spare decoders is stored; a comparison circuit for making a comparison between stored information in the first storage circuits and the input address; a first output circuit for outputting a signal for activating any one of the plurality of spare-decoder control lines in accordance with output representing a result of the comparison made by the comparison circuit and stored information in the second storage circuits; a second output circuit for outputting a signal for selectively activating the plurality of spare-decoder selecting lines in accordance with stored information in the third storage circuits when any one of the plurality of spare-decoder control lines is activated; and a third output circuit for outputting a signal for activating any one of the plurality of normal-decoder control lines in accordance with the output representing the result of the comparison made by the comparison circuit and the input address. The first storage circuits may comprise a plurality of first fuse devices for storing each bit data of the address of the defect memory cell to correspond to a state of cut/non-cut; the second storage circuits may comprise a second fuse device for storing information of the correspondence with two sets of sub-arrays such that one-bit data is caused to correspond to the state of cut/non-cut; the third storage circuits may comprise a third fuse device for storing each bit data of encode data indicating the correspondence with the plurality of spare decoders to correspond to the state of cut/non-cut; the first output circuit may be a first logical circuit which is complementarily activated by data stored in the second fuse device and data acquired by inverting the stored data when coincidence has been detected by the comparison circuit to activate either of two spare decoder control lines; the second output circuit may be a decoder which decodes encode data stored in the plurality of third fuse devices when coincidence has been detected by the comparison circuit so as to selectively activate the plurality of spare-decoder control line, and the third output circuit may be a second logical circuit which is complementarily activated in response to a predetermined bit signal of the input address and a signal acquired by inverting the predetermined bit signal when non-coincidence has been detected by the comparison circuit so as to activate either of two normal-decoder control lines. The first logical circuit may comprise a first AND gate for calculating a logical product of a detection output when coincidence has been detected by the comparison circuit and data stored in the second fuse device and a second AND gate for calculating the logical product of a detection output when coincidence has been detected by the comparison circuit and inverted data of data stored in the second fuse device, and the second logical circuit may comprise a third AND gate for calculating a logical product of detection output when non-coincidence has been detected by the comparison circuit and the predetermined bit signal of the input address and a fourth AND gate for calculating a logical product of a detection output when non-coincidence has been detected by the comparison circuit and an inverted signal of the predetermined bit signal of the input address.
In the semiconductor memory device according to the fifth aspect of the present invention, the assigning circuits may comprise a memory circuit in which the address of the defect memory cell is previously stored, which makes a comparison between the input address and the stored address of the defect memory cell, which outputs a signal for selectively activating the plurality of spare-decoder control lines when coincidence has been detected and which outputs a signal for activating the plurality of normal-decoder control lines when non-coincidence has been detected. The memory circuit may be provided with only one corresponding spare decoder and may comprise first storage circuits for storing the address of the defect memory cell; second storage circuits in which information of the correspondence with the sub-arrays of the plurality of sets constituting the plurality of memory banks is stored; a comparison circuit for making a comparison between stored information in the first storage circuits and the input address; a first output circuit for outputting a signal for activating any one of the plurality of spare-decoder control lines in accordance with an output representing a result of a comparison made by the comparison circuit and stored information in the second storage circuits; a second output circuit for outputting a signal for activating the corresponding spare decoder when any one of the plurality of spare-decoder control lines is activated; and a third output circuit for outputting a signal for activating any one of the plurality of normal-decoder control line in accordance with the output representing the result of the comparison made by the comparison circuit and in response to a predetermined bit signal at the input address.
In the semiconductor memory device according to the fifth aspect of the present invention, the sub-array may comprises a sub-cell array portion having word lines, spare word lines, bit-line pairs and memory cells disposed to correspond to each intersection of the word lines, the spare word lines and the bit-line pairs; equalizing circuit and sense amplifier lines including plurality of equalizing circuits disposed on the two sides of the sub-cell array and arranged to be controlled in response to an equalizing signal to equalize the bit-line pairs to a bit-line-pair equalization potential and a plurality of sense amplifiers for sense-amplifying data read from a memory cell on a selected row to the bit line; and a control circuit to which signals are input from the bank selecting line, the normal-decoder control line and the spare-decoder control line, which controls equalizing circuits corresponding to all of the sub-arrays in the same bank to an equalizing suspended state when activation of the bank is started so as to temporarily control the sense amplifier to an activation preparing state, and which is structured such that when any one of the plurality of normal-decoder control lines and the plurality of spare-decoder control lines has been activated, the equalizing circuits corresponding to the sub-arrays to be activated are controlled to maintain the equalizing suspended state so as to maintain the activation preparing state of the sense amplifiers and the equalizing circuits corresponding to the sub-arrays to be deactivated are returned to the equalizing state so as to restore the sense amplifiers to the deactivate state. The control circuit may comprise a first circuit to which a signal is input from the bank selecting line and which generates a pulse signal having a time width shortened in synchronization with the front edge; a first NMOS transistor having a gate to which an output signal from the first circuit is input; a PMOS transistor connected between the drain of the first NMOS transistor and a power-supply node and having a gate to which a signal is input from the bank selecting line; a second NMOS transistor connected between the source of the first NMOS transistor and a ground node and having a gate to which a signal is input from the normal-decoder control line; a third NMOS transistor connected between the source of the first NMOS transistor and the ground node and having a gate to which a signal is input from the spare-decoder control line; a latch circuit for latching the drain potential of the first NMOS transistor; and a logical gate for performing a logical process of an output signal from the latch circuit and an input signal from the bank selecting line to output an equalizing control signal for the equalizing circuit.
In the semiconductor memory device according to the fifth aspect of the present invention, the sub-array may comprises a sub-cell array portion having word lines, spare word lines, bit-line pairs and memory cells disposed to correspond to each intersection of the word lines, the spare word lines and the bit-line pairs; a plurality of equalizing circuits disposed on the two sides of the sub-cell array portion and arranged to be controlled in response to an equalizing signal to equalize the bit-line pairs to a bit-line-pair equalization potential; an array selecting switch connected between a sense amplifier line including a plurality of bit-line sense amplifiers which are disposed between adjacent sub-arrays and commonly used between adjacent sub-arrays and each of the bit-line pairs; and a control circuit to which signals are input from the bank selecting line, the normal-decoder control line and the spare-decoder control line, which controls the equalizing circuits corresponding to all of the sub-array in the same bank to an equalizing suspended state and brings the array selecting switch to a connection suspended state so that the sense amplifiers is temporarily brought to an activation preparing state when activation of the bank is started, and which maintains the equalizing circuit corresponding to the sub-array to be activated at an equalizing suspended state, controls the array selecting switch of adjacent sub-cell array to a connection suspended state so as to maintain the activation preparing state of the sense amplifier, controls the equalizing circuits corresponding to the residual sub-arrays to be deactivated to an equalizing state, and controls the array selecting switch to a connected state so as to return the sense amplifier to deactivated state when any one of the plurality of normal-decoder control lines and the plurality of spare-decoder control lines has been activated. The control circuit may comprise a first circuit to which a signal is input from the bank selecting line and which generates a pulse signal having a time width shortened in synchronization with the front edge; a first NMOS transistor having a gate to which an output signal from the first circuit is input; a PMOS transistor connected between the drain of the first NMOS transistor and a power-supply node and having a gate to which a signal is input from the bank selecting line; a second NMOS transistor connected between the source of the first NMOS transistor and a ground node and having a gate to which a signal is input from the normal-decoder control line; a third NMOS transistor connected between the source of the first NMOS transistor and the ground node and having a gate to which a signal is input from the spare-decoder control line; a latch circuit for latching the drain potential of the first NMOS transistor; and a logical gate for performing a logical process of an output signal from the latch circuit and an input signal from the bank selecting line to output an equalizing control signal for the equalizing circuit.
According to a sixth aspect of the present invention, there is provided a semiconductor memory device comprising a memory bank formed by dividing a memory cell array into a plurality of sections; a plurality of spare elements which are provided for each memory bank and arranged to be substituted for defect memory cells; a plurality of normal decoders disposed to correspond to the memory banks and arranged to select the row of the memory bank in accordance with an input address; a plurality of spare decoders provided to correspond to the memory banks and arranged to correspondingly operate the plurality of spare elements; a plurality of bank selecting lines for selectively instructing the plurality of memory banks; a spare-decoder control line for selectively instructing the spare decoder of the normal decoders and the spare decoders; a plurality of spare-decoder selecting lines for alternatively and selectively controlling the spare decoders of each memory bank; and assigning circuits provided by a number smaller than the total number of the spare elements and arranged to arbitrarily select and substitute one or plurality of spare elements for the defect memory cell.
In the semiconductor memory device according to the sixth aspect of the present invention, the assigning circuits may comprise a memory circuit in which the address of one or plural defect memory cells and information of the relationship between the address of the defect memory cell and the spare decoders in one-to-one correspondence is previously stored, which makes a comparison between the input address and the stored address of one or plural defect memory cells, which outputs a signal for correspondingly activating deviating the spare-decoder control line when coincidence/non-coincidence has been detected and which outputs a signal for selectively activating the plurality of spare-decoder selecting lines in accordance with information of the relationship between the address of the defect memory and the spare decoder when coincidence has been detected the memory circuit may comprise first storage circuits in which one or a plurality of addresses of the defect memory cell; a comparison circuit for making a comparison between information stored in the first storage circuits and the input address; a first output circuit for outputting a signal for activating the spare-decoder control line in accordance with an output produced when the comparison circuit has detected coincidence; second storage circuits in which information of one-to-one correspondence between the plurality of spare decoders and the address of the defect memory cell; and a second output circuit for outputting a signal for selectively activating the plurality of spare-decoder selecting lines in accordance with information stored in the second storage circuits and in response to at least a lowest bit of the address for use in substitution when the spare-decoder control line is activated. The addresses of the plurality of defect memory cells which are stored in the first storage circuits of the semiconductor memory device may be two to four types of addresses which are different from one another in only a lowest bit of the address for use in substitution or only two bits consisting of the lowest bit and one upper bit, and the one bit or two-bit address bits different from one another may be contained in the input of the second output circuit. The first storage circuits may comprise a plurality of first fuse devices for storing a lowest bit signal of the address for use to substitute the defect memory cell, a reversed signal of the lowest bit signal and each bit data upper than the lowest bit such that correspondence to cut/non-cut state is established; the second storage circuits may comprise a second fuse device for storing each bit data of encode data indicating the correspondence with the plurality of spare decoders except for the lowest bit such that correspondence to cut/non-cut state is established; the first output circuit may comprises a first comparison circuit for making a comparison among the lowest bit signal of the address for use in the substitution, a reversed signal of the lowest bit signal and data corresponding to the signals and stored in the first storage circuits, a second comparison circuit for making a comparison among each bit data upper than the lowest bit of the address and data corresponding to each bit data stored in the first storage circuits, and a first AND gate for performing a logical process of an output representing a result of the comparison made by the first comparison circuit and an output representing a result of the comparison made by the second comparison circuit to output a signal for activating the spare-decoder control line; and the second output circuit may be a decoder to which lowest-bit data of the address and data stored in the second storage circuits are input and which decodes the input data to selectively activate the plurality of spare-decoder selecting lines. The first storage circuits may comprise a plurality of first fuse devices for storing a lowest bit signal of the address for use to substitute the defect memory cell, a reversed signal of the lowest bit signal and each bit data upper than the lowest bit such that correspondence to cut/non-cut state is established; the second storage circuits may comprise a second fuse device for storing each bit data of encode data indicating the correspondence with the plurality of spare decoders such that correspondence to cut/non-cut state is established; the first output circuit may comprise a first comparison circuit for making a comparison among the lowest bit signal of the address for use in the substitution, a reversed signal of the lowest bit signal and data corresponding to the signals and stored in the first storage circuits, a second comparison circuit for making a comparison among each bit data upper than the lowest bit of the address and data corresponding to each bit data and stored in the first storage circuits, and a first AND gate for performing a logical process of an output representing a result of the comparison made by the first comparison circuit and an output representing a result of the comparison made by the second comparison circuit to output a signal for activating the spare-decoder control line; and the second output circuit is a decoder to which encode data stored in the second storage circuits or encode data obtained by switching the lowest bit data of the encode data item into lowest bit data of the address for use in the substitution is input and which decodes input encode data to selectively activating the plurality of spare-decoder selecting lines. The first storage circuits may comprise a plurality of first fuse devices for storing two bit signals from the lowest bit of the address for use to substitute the defect memory cell, reversed signals of the two bit signals and each bit data upper than the two bits such that correspondence to cut/non-cut state is established; the second storage circuits may comprise a second fuse device for storing each bit data of encode data indicating the correspondence with the plurality of spare decoders such that correspondence to cut/non-cut state is established; the first output circuit may comprise a first comparison circuit for making a comparison among the two bit signals from the lowest bit of the address for use in the substitution, reversed signals of the two bit signals and data corresponding to the signals and stored in the first storage circuits, a second comparison circuit for making a comparison among each bit data upper than the two bits from the lowest bit of the address and data corresponding to the each bit data and stored in the first storage circuits, and a first AND gate for performing a logical process of an output representing a result of the comparison made by the first comparison circuit and an output representing a result of the comparison made by the second comparison circuit to output a signal for activating the spare-decoder control line; and the second output circuit is a decoder to which encode data stored in the second storage circuits or encode data obtained by switching at least one bit of two bit data from the lowest bit into bit data to which the address corresponds is input and which decodes input encode data to selectively activate the plurality of spare-decoder selecting lines.
In the semiconductor memory device according to the sixth aspect of the present invention, the semiconductor memory device may further comprise a normal decoder control line for substantially instructing the normal decoder of the normal decoder and the spare decoder, wherein the memory circuit further incorporates a third output circuit for outputting a signal for activating the normal-decoder control line in accordance with an output made when non-coincidence has been detected by the comparison circuit.
Other objects, features and advantages of the invention will be evident from the following detailed description of the preferred embodiments described in conjunction with the attached drawings.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.